A magnetic random access memory (MRAM) is a type of a resistance change memory. As techniques for writing data to the MRAM, magnetic field writing and spin-transfer torque writing have been known. Among these techniques, the spin-transfer torque writing has advantages in higher integration, lower power consumption, and higher performance because of the property of a spin-transfer torque device that a smaller amount of a spin injection current is necessary for magnetization reversal as the size of magnetic bodies becomes smaller.
A spin-transfer torque MTJ (Magnetic Tunnel Junction) element has a stacked structure in which a nonmagnetic barrier layer (an insulating thin film) is sandwiched between two ferromagnetic layers, and stores data by a change in a magnetic resistance caused by spin-polarized tunneling. The MTJ element can be switched into a low resistance state or a high resistance state depending on the magnetization orientations of the two ferromagnetic layers. The MTJ element is in a low resistance state when the magnetization orientations (spin directions) of the two ferromagnetic layers are in a parallel state (a P state), and in a high resistance state when the magnetization orientations (spin directions) thereof are in an anti parallel state (an AP state).
Generally, a write current IP-AP for reversing the P state to the AP state is higher than a write current IAP-P for reversing the AP state to the P state. If a source line is biased to a higher voltage than a bit line when the write current IP-AP is applied to the MTJ element, the source voltage of a cell transistor increases due to the voltage drop of the MTJ element. Accordingly, the increased source voltage reduces the voltage difference between a source and a gate, and the back bias effect as well as this increased source voltage degrades the current driving capability of the cell transistor when the write IAP-P is applied to the MTJ element.
To solve these problems, it is conceived to stack the pinned layer and the free layer of the MTJ element in an inverse order. The MTJ element is normally configured to stack a free layer, a tunnel barrier, and a pinned layer from top down. By configuring the MTJ element to stack the pinned layer, the tunnel barrier, and the free layer from top down, the source line is biased to the higher voltage than the bit line when a relatively low write current IP-AP is applied. This can suppress the source voltage from increasing. However, with the configuration of the MTJ element to stack the pinned layer, the tunnel barrier, and the free layer from top down, the lower free layer is separated from a mask at the time of processing MTJ element, disadvantageously resulting in a variation in the size of the free layer among MTJ elements. The variation in the size of the free layer leads to variations in signals among memory cells.
Furthermore, it has been desired to downscale MRAMs like DRAMs.